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[tds_menu_login guest_tdicon="td-icon-profile" logout_tdicon="td-icon-log-out" tdc_css="eyJhbGwiOnsibWFyZ2luLWJvdHRvbSI6IjAiLCJkaXNwbGF5IjoiIn19" toggle_txt_color="var(--news-hub-white)" menu_offset_top="eyJhbGwiOiIxOSIsImxhbmRzY2FwZSI6IjE3IiwicG9ydHJhaXQiOiIxNSJ9" menu_offset_horiz="eyJhbGwiOi02LCJsYW5kc2NhcGUiOiItMyIsInBvcnRyYWl0IjoiLTIifQ==" menu_horiz_align="content-horiz-right" menu_bg="var(--news-hub-black)" menu_uh_color="var(--news-hub-light-grey)" menu_uh_border_color="var(--news-hub-dark-grey)" menu_ul_link_color="#ffffff" menu_ul_link_color_h="var(--news-hub-accent-hover)" menu_ul_sep_color="var(--news-hub-dark-grey)" menu_uf_txt_color="var(--news-hub-white)" menu_uf_txt_color_h="var(--news-hub-accent-hover)" menu_uf_border_color="var(--news-hub-dark-grey)" f_uh_font_family="325" f_uh_font_line_height="1.3" f_links_font_family="325" f_links_font_line_height="1.3" f_uf_font_line_height="1.3" f_uf_font_family="325" menu_uh_padd="eyJhbGwiOiIyMHB4IDI1cHggMThweCIsImxhbmRzY2FwZSI6IjE1cHggMjBweCAxM3B4IiwicG9ydHJhaXQiOiIxMHB4IDE1cHggOHB4In0=" menu_ul_padd="eyJhbGwiOiIxOHB4IDI1cHgiLCJsYW5kc2NhcGUiOiIxNnB4IDIwcHgiLCJwb3J0cmFpdCI6IjhweCAxNXB4In0=" menu_ul_space="eyJhbGwiOiIxMCIsImxhbmRzY2FwZSI6IjgiLCJwb3J0cmFpdCI6IjYifQ==" menu_ulo_padd="eyJhbGwiOiIxOHB4IDI1cHggMjBweCIsImxhbmRzY2FwZSI6IjEzcHggMjBweCAxNXB4IiwicG9ydHJhaXQiOiI4cHggMTVweCAxMHB4In0=" menu_shadow_shadow_size="0" menu_arrow_color="rgba(255,255,255,0)" menu_width="eyJhbGwiOiIyMjAiLCJwb3J0cmFpdCI6IjE4MCJ9" show_version="" menu_gh_padd="eyJhbGwiOiIyMHB4IDI1cHggMThweCIsImxhbmRzY2FwZSI6IjE1cHggMjBweCAxM3B4IiwicG9ydHJhaXQiOiIxMHB4IDE1cHggOHB4In0=" menu_gc_padd="eyJhbGwiOiIxOHB4IDI1cHggMjBweCIsImxhbmRzY2FwZSI6IjEzcHggMjBweCAxNXB4IiwicG9ydHJhaXQiOiI4cHggMTVweCAxMHB4In0=" menu_gh_color="var(--news-hub-light-grey)" menu_gh_border_color="var(--news-hub-dark-grey)" f_gh_font_family="325" menu_gc_btn1_bg_color="var(--news-hub-accent)" menu_gc_btn1_bg_color_h="var(--news-hub-accent-hover)" menu_gc_btn2_color="var(--news-hub-accent)" menu_gc_btn2_color_h="var(--news-hub-accent-hover)" f_btn1_font_family="325" f_btn1_font_transform="uppercase" f_btn2_font_family="325" f_btn2_font_transform="uppercase" f_btn1_font_weight="700" f_btn2_font_weight="700" show_menu="yes" f_uf_font_size="eyJsYW5kc2NhcGUiOiIxMiIsInBvcnRyYWl0IjoiMTIifQ==" icon_color="var(--news-hub-white)" icon_size="eyJhbGwiOjIyLCJsYW5kc2NhcGUiOiIyMCIsInBvcnRyYWl0IjoiMTgifQ==" avatar_size="eyJhbGwiOiIyMiIsImxhbmRzY2FwZSI6IjIwIiwicG9ydHJhaXQiOiIxOCJ9" ia_space="eyJhbGwiOiIxMCIsImxhbmRzY2FwZSI6IjgiLCJwb3J0cmFpdCI6IjYifQ==" f_toggle_font_family="325" f_toggle_font_size="eyJhbGwiOiIxNCIsImxhbmRzY2FwZSI6IjEzIiwicG9ydHJhaXQiOiIxMiJ9" logout_size="eyJhbGwiOjE0LCJsYW5kc2NhcGUiOiIxMyJ9" f_uh_font_size="eyJsYW5kc2NhcGUiOiIxMyIsInBvcnRyYWl0IjoiMTIifQ==" f_links_font_size="eyJsYW5kc2NhcGUiOiIxMyIsInBvcnRyYWl0IjoiMTIifQ==" f_gh_font_size="eyJsYW5kc2NhcGUiOiIxMyIsInBvcnRyYWl0IjoiMTIifQ=="]

Intel Could Dish Out An Estimated 365,000 Next-Gen Meteor Lake CPU Tiles Per Month

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Intel Estimated To Produce 365,000 Next-Gen Meteor Lake CPU Tiles Per Month 1

Intel's Meteor Lake CPU lineup is set to be a significant breakthrough for the company and we have some insights from ASCII who estimate just how many chips CPU tiles can be secured each month to supply to end-users.

Intel's Next-Gen Meteor Lake CPU Tiles In Production For Future Client PC Platforms

In a Q&A session with Intel officials, it was revealed that the "Intel 4" manufacturing process has seen obstacles with mass manufacturing, with limited facilities having the capability to fabricate the process. It was disclosed that "Intel 4" is in mass production at the D1 division Oregon facility, with total output reaching 40,000 monthly wafers. While the company has expressed confidence in its "Intel 4" process node, they also plan to set up other facilities as well since there is still uncertainty surrounding the supply.

Image Credits: ASCII

The folks at ASCII got to see a close-up of the Intel Meteor Lake CPU tile wafer. The size of the entire Meteor Lake tile (base tile) is estimated to be 23.1mm x 11.5mm. The CPU tile is reportedly around 8.9 x 8.3 mm or 73.9 mm2 (estimation not final), which leads to the conclusion that approximately 730 tiles in total can be obtained by a single wafer.

Moving to the crux, if we estimate a 50% yield rate of Intel 4 (which isn't confirmed yet), that leads to 365 CPU chips through a single wafer. If Intel reaches 1000 unit wafer output per month, that leads to 365,000 CPU tiles. One shouldn't worry about other tiles such as GPU, since those are based on TSMC's N5 and N6 processes, both of which have reached to a proficient level.

Close-up of Intel's Meteor Lake CPUs (the yellow spot is the CPU tile). (Image Source: ASCII)

As for whether this is a good figure or not, it is stated that it should be sufficient for the laptop masses but not optimal for desktop chips which may explain why the CPUs got canned in the first place. That said, Intel's 6+8 Desktop CPUs were rumored to be using a repurposed Meteor Lake-P die. Intel is expected to unveil some more details of Meteor Lake CPUs at Hot Chips today followed by an official introduction next month at the Innovation event. The actual launch is said to take place this fall.

Intel Mobility CPU Lineup:

CPU FamilyLunar LakeArrow LakeMeteor LakeRaptor LakeAlder Lake
Process Node (CPU Tile)Intel 18A?Intel 20A '5nm EUV"Intel 4 '7nm EUV'Intel 7 '10nm ESF'Intel 7 '10nm ESF'
Process Node (GPU Tile)TSMC 3nm?TSMC 3nmTSMC 5nmIntel 7 '10nm ESF'Intel 7 '10nm ESF'
CPU ArchitectureHybridHybrid (Four-Core)Hybrid (Triple-Core)Hybrid (Dual-Core)Hybrid (Dual-Core)
P-Core ArchitectureTBDLion CoveRedwood CoveRaptor CoveGolden Cove
E-Core ArchitectureTBDSkymontCrestmontGracemontGracemont
Top ConfigurationTBDTBD6+8 (H-Series)6+8 (H-Series)
8+16 (HX-Series)
6+8 (H-Series)
8+8 (HX-Series)
Max Cores / ThreadsTBDTBD14/2014/2014/20
Planned LineupU Series?H/P/U SeriesH/P/U SeriesH/P/U SeriesH/P/U Series
GPU ArchitectureXe2-LPG (Battlemage)Xe-LPG (Alchemist)Xe-LPG (Alchemist)Iris Xe (Gen 12)Iris Xe (Gen 12)
GPU Execution Units64 EUs192 EUs128 EUs (1024 Cores)96 EUs (768 Cores)96 EUs (768 Cores)
Memory SupportTBDTBDDDR5-5600
LPDDR5-7400
LPDDR5X - 7400+
DDR5-5200
LPDDR5-5200
LPDDR5-6400
DDR5-4800
LPDDR5-5200
LPDDR5X-4267
Memory Capacity (Max)TBDTBD96 GB64 GB64 GB
Thunderbolt 4 PortsTBDTBD444
WiFi CapabilityTBDTBDWiFi 6EWiFi 6EWiFi 6E
TDPTBDTBD7W-45W15-55W15-55W
Launch~20252H 20242H 20231H 20231H 2022
Written by Muhammad Zuhair

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