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[tds_menu_login guest_tdicon="td-icon-profile" logout_tdicon="td-icon-log-out" tdc_css="eyJhbGwiOnsibWFyZ2luLWJvdHRvbSI6IjAiLCJkaXNwbGF5IjoiIn19" toggle_txt_color="var(--news-hub-white)" menu_offset_top="eyJhbGwiOiIxOSIsImxhbmRzY2FwZSI6IjE3IiwicG9ydHJhaXQiOiIxNSJ9" menu_offset_horiz="eyJhbGwiOi02LCJsYW5kc2NhcGUiOiItMyIsInBvcnRyYWl0IjoiLTIifQ==" menu_horiz_align="content-horiz-right" menu_bg="var(--news-hub-black)" menu_uh_color="var(--news-hub-light-grey)" menu_uh_border_color="var(--news-hub-dark-grey)" menu_ul_link_color="#ffffff" menu_ul_link_color_h="var(--news-hub-accent-hover)" menu_ul_sep_color="var(--news-hub-dark-grey)" menu_uf_txt_color="var(--news-hub-white)" menu_uf_txt_color_h="var(--news-hub-accent-hover)" menu_uf_border_color="var(--news-hub-dark-grey)" f_uh_font_family="325" f_uh_font_line_height="1.3" f_links_font_family="325" f_links_font_line_height="1.3" f_uf_font_line_height="1.3" f_uf_font_family="325" menu_uh_padd="eyJhbGwiOiIyMHB4IDI1cHggMThweCIsImxhbmRzY2FwZSI6IjE1cHggMjBweCAxM3B4IiwicG9ydHJhaXQiOiIxMHB4IDE1cHggOHB4In0=" menu_ul_padd="eyJhbGwiOiIxOHB4IDI1cHgiLCJsYW5kc2NhcGUiOiIxNnB4IDIwcHgiLCJwb3J0cmFpdCI6IjhweCAxNXB4In0=" menu_ul_space="eyJhbGwiOiIxMCIsImxhbmRzY2FwZSI6IjgiLCJwb3J0cmFpdCI6IjYifQ==" menu_ulo_padd="eyJhbGwiOiIxOHB4IDI1cHggMjBweCIsImxhbmRzY2FwZSI6IjEzcHggMjBweCAxNXB4IiwicG9ydHJhaXQiOiI4cHggMTVweCAxMHB4In0=" menu_shadow_shadow_size="0" menu_arrow_color="rgba(255,255,255,0)" menu_width="eyJhbGwiOiIyMjAiLCJwb3J0cmFpdCI6IjE4MCJ9" show_version="" menu_gh_padd="eyJhbGwiOiIyMHB4IDI1cHggMThweCIsImxhbmRzY2FwZSI6IjE1cHggMjBweCAxM3B4IiwicG9ydHJhaXQiOiIxMHB4IDE1cHggOHB4In0=" menu_gc_padd="eyJhbGwiOiIxOHB4IDI1cHggMjBweCIsImxhbmRzY2FwZSI6IjEzcHggMjBweCAxNXB4IiwicG9ydHJhaXQiOiI4cHggMTVweCAxMHB4In0=" menu_gh_color="var(--news-hub-light-grey)" menu_gh_border_color="var(--news-hub-dark-grey)" f_gh_font_family="325" menu_gc_btn1_bg_color="var(--news-hub-accent)" menu_gc_btn1_bg_color_h="var(--news-hub-accent-hover)" menu_gc_btn2_color="var(--news-hub-accent)" menu_gc_btn2_color_h="var(--news-hub-accent-hover)" f_btn1_font_family="325" f_btn1_font_transform="uppercase" f_btn2_font_family="325" f_btn2_font_transform="uppercase" f_btn1_font_weight="700" f_btn2_font_weight="700" show_menu="yes" f_uf_font_size="eyJsYW5kc2NhcGUiOiIxMiIsInBvcnRyYWl0IjoiMTIifQ==" icon_color="var(--news-hub-white)" icon_size="eyJhbGwiOjIyLCJsYW5kc2NhcGUiOiIyMCIsInBvcnRyYWl0IjoiMTgifQ==" avatar_size="eyJhbGwiOiIyMiIsImxhbmRzY2FwZSI6IjIwIiwicG9ydHJhaXQiOiIxOCJ9" ia_space="eyJhbGwiOiIxMCIsImxhbmRzY2FwZSI6IjgiLCJwb3J0cmFpdCI6IjYifQ==" f_toggle_font_family="325" f_toggle_font_size="eyJhbGwiOiIxNCIsImxhbmRzY2FwZSI6IjEzIiwicG9ydHJhaXQiOiIxMiJ9" logout_size="eyJhbGwiOjE0LCJsYW5kc2NhcGUiOiIxMyJ9" f_uh_font_size="eyJsYW5kc2NhcGUiOiIxMyIsInBvcnRyYWl0IjoiMTIifQ==" f_links_font_size="eyJsYW5kc2NhcGUiOiIxMyIsInBvcnRyYWl0IjoiMTIifQ==" f_gh_font_size="eyJsYW5kc2NhcGUiOiIxMyIsInBvcnRyYWl0IjoiMTIifQ=="]

Intel’s Next-Gen Lunar Lake CPU Spotted: Early Sample With 20 Cores, 3.9 GHz Boost Clocks, 16 MB L3 Cache

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A super-early Intel Lunar Lake CPU has been spotted within the SiSoftware database which packs 20 cores and up to 3.9 GHz boost clocks.

Intel Lunar Lake CPUs Are Up & Running: 20 Core Engineering Sample Spotted With Up To 3.91 GHz Clocks

At Innovation 2023, Intel showcased the very first demo of an early Lunar Lake CPU which booted into the operating system and was running an AI workload, showcasing its stability. Now, the same Lunar Lake CPUs are showing up in online databases with one early sample making its way to the SiSoftware database.

The Intel Lunar Lake CPU sample was recently added to the database (3rd October 2023) so it may as well be the same chip that we saw during the event. As for specifications, the Lunar Lake ES chip comes packed with 20 cores which operate at a base frequency of 1.0 GHz and a boost frequency of 3.91 GHz for the P-Core and 2.61 GHz for the E-Core cluster.

It was recently reported that Lunar Lake CPUs will retain the Lion Cove P-Core and Skymont E-Core architecture which is the same that is used for Arrow Lake chips. It is also likely that the compute tile will be based on the 20A process.

The chip features 10 MB of L2 cache for the P-Core clusters and 4 MB of L2 cache for the E-Core clusters for a combined total of 14 MB L2 cache. The entire chip features a shared 16 MB L3 cache too. That's 25% higher L2 cache for the P-Cores versus the upcoming Redwood Cove cores which are equipped with 2 MB L2 cache per core. But at the moment it is too early to tell what the final core/thread count of this chip would be and how they will be split between the P-Cores & E-Cores.

The Intel Lunar Lake CPU was running at an average power of 17W since the lineup is focusing on the mobility segment with improved performance/watt gains. The CPU itself was running on Intel's Reference Evaluation Platform with LPDDR5 memory and is marked as a LNL-M chip. The chip was tested in the Processor Cryptography (High Security) workload and despite its super early nature, it managed to come out on par with Intel's top Tiger Lake chip, the i7-1195G7, with similar bandwidth results.

Intel's Lunar Lake CPUs are targeting production in the second half of 2024 followed by a launch in 2025. The chips will be replacing Arrow Lake as the next-gen mobility family and we can expect a few big upgrades, especially in the graphics department which will be upgraded to the next-gen Xe2 or Battlemage architecture.

Intel Mobility CPU Lineup:

CPU FamilyLunar LakeArrow LakeMeteor LakeRaptor LakeAlder Lake
Process Node (CPU Tile)Intel 20A?Intel 20A '5nm EUV"Intel 4 '7nm EUV'Intel 7 '10nm ESF'Intel 7 '10nm ESF'
Process Node (GPU Tile)TSMC 3nm?TSMC 3nmTSMC 5nmIntel 7 '10nm ESF'Intel 7 '10nm ESF'
CPU ArchitectureHybridHybrid (Four-Core)Hybrid (Triple-Core)Hybrid (Dual-Core)Hybrid (Dual-Core)
P-Core ArchitectureLion Cove?Lion CoveRedwood CoveRaptor CoveGolden Cove
E-Core ArchitectureSkymont?SkymontCrestmontGracemontGracemont
LP E-Core Architecture (SOC)Skymont?Crestmont?Crestmont?N/AN/A
Top ConfigurationTBDTBD6+8 (H-Series)6+8 (H-Series)
8+16 (HX-Series)
6+8 (H-Series)
8+8 (HX-Series)
Max Cores / ThreadsTBDTBD14/2014/2014/20
Planned LineupU Series?H/P/U SeriesH/P/U SeriesH/P/U SeriesH/P/U Series
GPU ArchitectureXe2-LPG (Battlemage)Xe-LPG (Alchemist)Xe-LPG (Alchemist)Iris Xe (Gen 12)Iris Xe (Gen 12)
GPU Execution Units64 EUs192 EUs128 EUs (1024 Cores)96 EUs (768 Cores)96 EUs (768 Cores)
Memory SupportTBDTBDDDR5-5600
LPDDR5-7400
LPDDR5X - 7400+
DDR5-5200
LPDDR5-5200
LPDDR5-6400
DDR5-4800
LPDDR5-5200
LPDDR5X-4267
Memory Capacity (Max)TBDTBD96 GB64 GB64 GB
Thunderbolt 4 PortsTBDTBD444
WiFi CapabilityTBDTBDWiFi 6EWiFi 6EWiFi 6E
TDPTBDTBD7W-45W15-55W15-55W
Launch~20252H 20242H 20231H 20231H 2022
Written by Hassan Mujtaba

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